Multi Operand Latency Efficient Binary Adder Using RNS for Low Dense Applications

Abstract

Addition is one of the most basic operations performed in all computing units, including
microprocessors and digital signal processors. It is also a basic unit utilized in various
complicated algorithms of multiplication and division. Efficient implementation of an adder
circuit usually revolves around reducing the cost to propagate the carry between successive bit
positions. Hence, a new high-speed and area efficient adder architecture is proposed using
pre-compute bitwise addition followed by carry prefix computation logic to perform the threeoperand
binary addition that consumes substantially less area, low power and drastically
reduces the adder delay. Further, this project is enhanced by using RNS adder to further
reduce more density and latency constraints. RNS introduces simple and low complex carry
skip logic to reduce parameters constraints.