Verilog HDL Implementation of Efficient Lossless EEG Compression Architecture Based on VLSI

Abstract

According to the work, an effective VLSI device's lossless EEG compression circuit
architecture is presented to improve the dependability and transmission capacity of EEG
signals. The proposed architecture has been given a novel lossless data compression method
that incorporates a casting-vote solution, a proposed neural prediction, and a quadra probability
compression codec. A static coding table with several Areas and Binary, for training encoders
employing the multiplexer's and comparator core elements, make up the mid equilibrium
encoder. A pipelining strategy was used to increase the suggested system's effectiveness.
Produce the suggested design, which calls for a 0.18 m CMOS device with 8215 gates working
at a 100MHz clock rate.The Compression is assisted by the Internet of Things, which is utilised
to send the signal generated by the EEG to the compression system. The proposed system
combined an IoT VLSI algorithm. In fact, transferring electroencephalography signal data
across a wireless network is a regularly employed tool for addressing stability and performance
issues.