16 Bit SRAM Design Using Quantum Dot Cellular Automata Technology

Resumen

At present, the widely used in integrated circuit design in theVLSI industry is
Complementary Metal Oxide Semiconductor (CMOS) transistors. The VLSI industry is
progressing towards the design of high package density and less power consuming nano
scale devices. The CMOS technology cannot work efficiently at nano scale and the circuits
based on CMOS technology may also need more power for operation. There is a high
possibility for the efficient memory design in Quantum dot cellular automata technology.
The suggested methodology of 16 bit static RAM Design is deeply based on the QCA
technology with minimal delay , less area and low power consumption for operation. This
paper affords the design methodology of a 16bit static RAM and its execution with a new
dimension in QCA. The pipelining architecture in QCA enables the SRAM to perform
more faster in executing operations. Memory sizes can also be increased in this type of
design .The 2x1 multiplexer and the 16:1 decoder circuits in QCA technology works with
minimal delay and it enhances the signal distribution network. Therefore the proposed
SRAM is more efficient in all aspects in an integerated circuit design. The suggested
SRAM is designed using QCA Designer E tool.