Low Density and Latency Optimized Scalable Binary Counter/Compressor using Efficient Sorting Network

Resumen

Parallel counters are enter components in numerous number juggling circuits, particularly
quick multipliers. The summation of multiple operands in parallel forms part of the critical
path in various digital signal processing units. To speedup the summation, high compression
ratio counters and compressors are necessary. In this article, we present a novel method of
fast saturated binary counters and exact/approximate (4:2) compressors based on the sorting
network. The inputs of the counter are asymmetrically divided into two groups and fed into
sorting networks to generate reordered sequences, which can be solely represented by one-hot
code sequences. Between the reordered sequence and the one-hot code sequence, three
special Boolean equations are established, which can significantly simplify the output
Boolean expressions of the counter. Further, this project is enhanced by using parallel sorting
algorithms for finding/ sorting M largest values from N inputs and then design scalable
architectures based on proposed algorithms. For finding the largest values the iterative sorting
techniques also proposed.Bitonic Sorting Is one type of efficient such algorithm for
implementing with optimised parameters.